I'm worried 🙁 will be Rick rolled.. again

Hugz & xXx

No.

Me right now, but it's two horses grazing.

@MikeImBack @OrionKidder @zenheathen
Stalking PMJT is this nitwit's FT job. Quite sure the PM was not surprised to meet him on a secluded beach while on vacation. By patiently talking to him and not walking away JT changed the channel and delivered the opposite of what Bexte expected. Lets see what's clips Bexte "cherry-picks".

@MikeImBack @zenheathen That's exactly what he'll do, stumble on a rock, on purpose, and then say Trudeau tripped him.

What I hate is that it puts me in the position of in effect defending Trudeau. I really hate him--his lies, his smugness, his betrayal of Indigenous people, his broken promises--but conservatives don't attack that stuff because THEY LIKE IT, so they resort to bullshit.

OK, fixed that - incorrect settings on some DMA registers I think?

Next problem: about 0.1% of packets are being corrupted in an interesting way (one 32-bit word of gibberish injected in the IP header).

Looking in the ILA, I see two different things going on that might be related.

First, the APB PSEL signal is being asserted for several cycles after PREADY goes high. It should go low the same time that PENABLE does; this is likely a bug in my pipeline register stage block.

Second, there's some weird timing on PSEL vs PENABLE right at the cursor.

What we've got going on here is a sequence of writes to the transmit FIFO triggered by DMA: PADDR=20 24, (gap), 28, 2c.

But we also have what appears to be a write to 800 followed by some reads of 840.

The reads of 840 are probably the CPU polling some other peripheral. I can probably play with AXI arbitration priorities to ensure that the MDMA gets precedence and polling doesn't slow down the DMA transfer, but that's not a problem that should corrupt packets, just a slight performance hit.

The bug is right at the cursor; we have *two* writes to the FIFO at 0x028. Looking carefully, the first write is 0x00000000 and looks like it was supposed to be associated with the 0x800 PADDR.

I think this is actually a write to a different peripheral on the bus but address decoding screwed up due to the pipelining and asserted PSEL even though the transaction wasn't meant for us. The second write of 020a0657 is, I think, the correct value that's supposed to go here.

Ok so it looks like these bugs are unrelated.

The stretched PSEL signal is a problem in the pipeline register slice, while the other problem is caused by me writing PADDR too soon during a bus stall. Time to grab some more signals in the LA to confirm...

Ok, fixed both bugs.

With TX DMA active I'm now getting correct results, no dropped packets, and 327 Mbps of throughput.

The FMC bus is now at 62% utilization so I should theoretically be able to bump up quite a bit more without upping the FMC clock rate.

Ui, das sieht ja mal edel und schick aus 😊​.

Das ist wahrlich ein Kunstwerk! 😯🤗

hashtag spelling error ?

#Montmatre -> #Montmartre

@uherren Huhuuuuu 👋🏼 da war ich schon weg...also erst heute: Mooiiiiiiiin ❣️☕🥐🥐

@Kuestentroete Bonjour 😘💕💕 ☕🥐

Ich sende dir hier nich 3 weitere Bilder von den Wänden aus der alten Papierfabrik Attisholz / Solothurn.
Und wie ich vorgestern las, scheint in Estland eine grosse Ausstellung mit Streetartbildern eröffnet worden sein.

@uherren Ein lustiges Wochenende 😀 wünsche ich Dir 😘💕